description the a6812 device combines a 20-bit cmos shift register, ac com pa ny ing data latches and control cir cuit ry with bipolar sourcing out puts ,and pnp active pull-downs. de signed pri mar ily to drive vacuum-flu o res cent displays, the 60 v and -40 ma output ratings also allow these devices to be used in many other peripheral power driver applications. the a6812 features an increased data-input rate (com pared with the older ucn/ucq5812-f) and a controlled output slew rate. the cmos shift register and latches allow direct interfacing with mi cro pro ces sor-based systems. with a 3.3 or 5 v logic supply, they operate to at least 10 mhz. a cmos serial data output permits cascaded con nec tions in ap pli ca tions re quir ing additional drive lines. similar devices are avail able as the a6810 (10-bit) and a6818 (32-bit). the a6812 output source drivers are npn dar ling tons, capable of sourcing up to 40 ma. the controlled output slew rate reduces elec tro mag net ic noise, which is an important consideration in systems that include telecommunications and/or microprocessors and to meet government emis sions 26182.126f features and benefits ? controlled output slew rate ? high-speed data storage ? 60 v minimum output break down ? high data-input rate ? pnp active pull-downs ? low output-saturation voltages ? low-power cmos logic and latches ? improved replacements for tl5812x, ucn5812x, and ucq5812x dabic-iv 20-bit serial-input latched source driver continued on the next page? package: functional block diagram not to scale a6812 28-pin plcc (ep package) 28-pin soicw (package lw)
dabic-iv 20-bit serial-input latched source driver a6812 2 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com selection guide part number pb-free packing package ambient temperature, t a (c) a6812eeptr* ? 800 pieces/13-in. reel plcc ?40 to 85 a6812eeptr-t* yes a6812elwtr-t yes 1000 pieces/13-in. reel soic-w a6812klwtr-t* yes 1000 pieces/13-in. reel soic-w ?40 to 125 a6812septr* ? 800 pieces/13-in. reel plcc ?20 to 85 a6812septr-t yes a6812slwtr-t* yes 1000 pieces/13-in. reel soic-w * variant is in production but has been determined to be not for new design. this classification indicates that sale of the varia nt is currently restricted to existing customer applications. the variant should not be purchased for new design applications because obsolescence in the near future is probable. samples are no longer available. status change: may 4, 2009. regulations. for inter-digit blanking, all output drivers can be dis abled and all sink drivers turned on with a blank ing input high. the pnp active pull-downs sink at least 2.5 ma. three temperature ranges are available for optimum performance in commercial (suffix s-), industrial (suffix e-), or automotive (suffix k-) ap pli ca tions. pack age styles are provided for surface-mount soic (suffix -lw), or minimum-area surface-mount plcc (suffix -ep). copper lead frames, low logic-power dis si pa tion, and low output-saturation voltages allow these drivers to source 25 ma from all outputs continuously to more than 43c (suffix -lw) or 61c (suffix -ep). each package is available in a lead (pb) free version, with 100% matte tin leadframe plating. description (continued)
dabic-iv 20-bit serial-input latched source driver a6812 3 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com absolute maximum ratings* characteristic symbol notes rating units logic supply voltage v dd 7v driver supply voltage v bb 60 v input voltage range v in ?0.3 to v dd + 0.3 v continuous output current range i out ?40 to 15 ma operating ambient temperature t a range e ?40 to 85 oc range k ?40 to 125 oc range s ?20 to 85 oc maximum junction temperature t j (max) 150 oc storage temperature t stg ?65 to 125 oc *caution: these cmos devices have input static protection (class 2) but are still susceptible to damage if exposed to extremely high static electrical charges. thermal characteristics characteristic symbol test conditions* value units package thermal resistance r ja package ep, 1-layer pcb with solder limited to mounting pads 68 oc/w package lw, 1-layer pcb with solder limited to mounting pads 80 oc/w *additional thermal information available on the allegro website 50 75 100 125 150 2.5 0.5 0 allowable package power dissipation in watts ambient temperature in o o o o c 2.0 1.5 1.0 25 dwg. gp-024-2 suffix 'ep', r = 68 o c/w q ja o suffix 'lw', r = 80 c/ w q ja
dabic-iv 20-bit serial-input latched source driver a6812 4 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com typical input circuit typical output driver dwg. ep-010-5 in dd v v bb dwg. ep-021-19 out n 4 5 6 7 8 9 10 19 20 21 22 23 24 25 load supply bb v out 2 out 7 out 8 dwg. pp-029-7 out 19 out 18 out 13 12 13 14 27 28 17 18 serial data out blanking logic supply strobe ground clock clk st blnk out 9 out 10 out 12 out 11 11 latches register register latches 2 326 27 28 serial data in out 6 out 1 out 4 out 3 out 20 1 15 16 out 5 out 17 out 16 out 15 out 14 dd v ep package lw package 2 3 4 5 6 7 8 9 12 13 14 15 16 28 1 v dd dwg. pp-059-1 out 10 out 20 out 11 out 19 register latches v bb clock st clk 26 27 22 23 24 25 serial data out load supply serial data in 10 11 strobe ground logic supply 19 20 21 blanking 17 18 out 9 out 1 out 2 out 8 out 18 out 12 latches register
dabic-iv 20-bit serial-input latched source driver a6812 5 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com truth table serial shift register contents serial latch contents output con tents data clock data strobe input input i 1 i 2 i 3 ... i n-1 i n output input i 1 i 2 i 3 ... i n-1 i n blanklng i 1 i 2 i 3 ... i n-1 i n h h r 1 r 2 ... r n-2 r n-1 r n-1 l l r 1 r 2 ... r n-2 r n-1 r n-1 x r 1 r 2 r 3 ... r n-1 r n r n x x x ... x x x l r 1 r 2 r 3 ... r n-1 r n p 1 p 2 p 3 ... p n-1 p n p n h p 1 p 2 p 3 ... p n-1 p n l p 1 p 2 p 3 ... p n-1 p n x x x ... x x h l l l ... l l l = low logic level h = high logic level x = irrelevant p = present state r = previous state
dabic-iv 20-bit serial-input latched source driver a6812 6 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com limits @ v dd = 3.3 v limits @ v dd = 5 v characteristic symbol test conditions mln. typ. max. min. typ. max. units output leakage current i cex v out = 0 v ? <-0.1 -15 ? <-0.1 -15 a output voltage v out(1) i out = -25 ma 57.5 58.3 ? 57.5 58.3 ? v v out(0) i out = 1 ma ? 1.0 1.5 ? 1.0 1.5 v output pull-down current i out(0) v out = 5 v to v bb 2.5 5.0 ? 2.5 5.0 ? ma input voltage v in(1) 2.2 ? ? 3.3 ? ? v v in(0) ? ? 1.1 ? ? 1.7 v input current i in(1) v in = v dd ? <0.01 1.0 ? <0.01 1.0 a i in(0) v in = 0 v ? <-0.01 -1.0 ? <-0.01 -1.0 a input clamp voltage v ik i in = -200 a ? -0.8 -1.5 ? -0.8 -1.5 v serial data output volt age v out(1) i out = -200 a 2.8 3.05 ? 4.5 4.75 ? v v out(0) i out = 200 a ? 0.15 0.3 ? 0.15 0.3 v maximum clock frequency f c 10* ? ? 10* ? ? mhz logic supply current i dd(1) all outputs high ? 0.25 0.75 ? 0.3 1.0 ma i dd(0) all outputs low ? 0.25 0.75 ? 0.3 1.0 ma load supply current i bb(1) all outputs high, no load ? 3.0 6.0 ? 3.0 6.0 ma i bb(0) all outputs low ? 0.2 20 ? 0.2 20 a blanking -to- output delay t dis(bq) c l = 30 pf, 50% to 50% ? 0.7 2.0 ? 0.7 2.0 s t en(bq) c l = 30 pf, 50% to 50% ? 1.8 3.0 ? 1.8 3.0 s strobe -to- output delay t p(sth-ql) r l = 2.3 k , c l 30 pf ? 0.7 2.0 ? 0.7 2.0 s t p(sth-qh) r l = 2.3 k , c l 30 pf ? 1.8 3.0 ? 1.8 3.0 s output fall time t f r l = 2.3 k , c l 30 pf 2.4 ? 12 2.4 ? 12 s output rise time t r r l = 2.3 k , c l 30 pf 2.4 ? 12 2.4 ? 12 s output slew rate dv/dt r l = 2.3 k , c l 30 pf 4.0 ? 20 4.0 ? 20 v/ s clock -to- serial data out delay t p(ch-sqx) i out = 200 a ? 50 ? ? 50 ? ns negative current is de ned as coming out of (sourcing) the speci ed device terminal. typical data is is for design information only and is at t a = +25c. * operation at a clock frequency greater than the speci ed minimum is possible but not warranteed. electrical characteristics at t a = +25c (a6812s-) or over operating tem per a ture range (a6812e- or a6812k-), v bb = 60 v; un less otherwise noted
dabic-iv 20-bit serial-input latched source driver a6812 7 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com timing requirements and specifications (logic levels are v dd and ground) serial data present at the input is trans ferred to the shift register on the logic ?0? to logic ?1? transition of the clock input pulse. on suc ceed ing clock pulses, the registers shift data information towards the serial data output. the serial data must appear at the input prior to the rising edge of the clock input waveform. information present at any register is transferred to the re- spective latch when the strobe is high (serial-to-par al lel con- ver sion). the latches will continue to accept new data as long as the strobe is held high. ap pli ca tions where the latches are bypassed (strobe tied high) will require that the blanking input be high during serial data entry. when the blanking input is high, the output source driv- ers are disabled (off); the pnp active pull-down sink drivers are on. the in for ma tion stored in the latches is not affected by the blanking input. with the blank ing input low, the outputs are con trolled by the state of their re spec tive latches. a. data active time before clock pulse (data set-up time), t su(d) ........................................ 25 ns b. data active time after clock pulse (data hold time), t h(d) ............................................. 25 ns c. clock pulse width, t w(ch) .............................................. 50 ns d. time between clock ac ti va tion and strobe, t su(c) ...... 100 ns e. strobe pulse width, t w(sth) ........................................... 50 ns note ? timing is representative of a 10 mhz clock. higher speeds may be attainable with increased supply voltage; op- er a tion at high temperatures will reduce the speci ed max i mum clock frequency. clock serial data in strobe blanking out n dwg. wp-029 50% serial data out data data 10% 90% 50% 50% 50% c a b d e low = all outputs enabled p(sth-ql) t p(ch-sqx) t data p(sth-qh) t blanking out n dwg. wp-030a data 10% 50% en(bq) t dis(bq) t high = all outputs blanked (disabled) r t f t 50% 90%
dabic-iv 20-bit serial-input latched source driver a6812 8 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com ep package, 28-pin plcc 2128 a dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown a terminal #1 mark area for reference only (reference jedec ms-018 ab) dimensions in millimeters 12.450.13 12.450.13 0.51 min c seating plane c 0.10 28x 11.510.08 5.210.36 5.210.36 0.740.08 5.210.36 0.430.10 5.210.36 11.510.08 0.51 1.27 4.37 +0.20 ?0.18
dabic-iv 20-bit serial-input latched source driver a6812 9 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com copyright ?2000-2009, allegro microsystems, inc. the products described here are manufactured under one or more u.s. patents or u.s. patents pending. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. for the latest version of this document, visit our website: www.allegromicro.com lw package, 28-pin soicw 17.900.20 10.300.33 7.500.10 c seating plane c 0.1 28x 1.27 0.20 0.10 2.65 max 0.25 4 4 0.27 +0.07 ?0.06 0.84 +0.44 ?0.43 2 1 28 gauge plane seating plane a b reference pad layout (reference ipc soic127p1030x265-28m) all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances for reference only (reference jedec ms-013 ae) dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown a terminal #1 mark area 0.41 0.10 b 2.20 0.65 9.60 1.27 pcb layout reference view 2 1 28
|
